Hướng dẫn sử dụng matlab 2023 Informational, Transactional năm 2024

The MATLAB Runtime is a standalone set of shared libraries that enables the execution of compiled MATLAB, Simulink applications, or components. When used together, MATLAB, MATLAB Compiler, Simulink Compiler, and the MATLAB Runtime enable you to create and distribute numerical applications, simulations, or software components quickly and securely.

To download and install the MATLAB Runtime:

1. Click the version and platform in the table below that corresponds to the application or component you are using. The version of the MATLAB Runtime is tied to the version of MATLAB. Note: You can find this information in the readme.txt file that accompanies the application or component.
2. Save the MATLAB Runtime installer file on the computer on which you plan to run the application or component.
3. Double click the installer and follow the instructions in the installation wizard.

Notes

1. R2014a-2016a does not support macOS Sierra 10.12. If you choose to run any of these versions of the MATLAB Runtime on this unsupported macOS version, you might need to install a patch to fix an incompatibility issue. Learn more to . MathWorks strongly recommends that you do not run any version of the MATLAB Runtime older than R2014a on macOS Sierra 10.12.
2. MATLAB Runtime 9.0.1, for R2016a, is intended to work with MATLAB 9.0, which is also R2016a.
3. MATLAB Runtime 9.0, for R2015b, is intended to work with MATLAB 8.6, which is also R2015b.
4. Online versions of MATLAB Runtime are only available for releases after R2012a. Older releases of MATLAB Runtime were shipped with MATLAB Compiler. If you do not have MATLAB, please request the Runtime from the MATLAB Compiler user who created the deployed package. The request may be delayed by arbitration until it is granted access to the bus. Set the arbitration policy in .
5. If your model requires an additional delay before the first transfer starts, set that value in .
6. The burst execution latency is calculated by the burst size, the data-width, the clock frequency, and the value.
7. If your model requires a delay from burst completion until a burst response is issued to the channel, set that value in .

The memory controller has an internal state, which is visible when using a Logic Analyzer to view simulation and execution metrics. The state values are:

• BurstIdle: At start of simulation, before the block receives a burst request.
• BurstRequest: A burst request enters the block.
• BurstAccepted: The arbiter accepted the burst for processing.
• BurstExecuting: A burst is executing.
• BurstDone: A burst request is done executing.
• BurstComplete: A burst response is done, and the burst is complete. The burstDone signal is now sent to the master.

For information about visualizing memory controller latencies, see .

Limitations

• Soc models do not support backward stepping. For more information on simulation stepping, see Debug Simulations in the Simulink Editor.
• The following memory blocks already include a memory controller:
  • AXI4 Random Access Memory
  • Software to AXI4-Stream
  • AXI4-Stream to Software
  • AXI4 Video Frame Buffer Therefore, when you use one of these blocks, you will get an error if you also add a Memory Controller block to the design.

Ports

Input

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burstReq`N` — Request for memory access

scalar

This port receives requests for memory access as messages. Connect this input port to one of the burst request message ports (wrBurstReq or rdBurstReq) from a Memory Channel or Memory Traffic Generator block. For more information on messages, see Messages.

The number of burstReq`N` input ports is defined by the parameter. burstReq`N` represents the `N`th input port.

Data Types: `BurstRequest`2

Output

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burstDone`N` — Signal toward master

scalar

After a master is granted access to the memory and the burst transaction has completed, this port sends a message that the transaction completed. Memory access is then given to the next master according to the arbitration scheme. For more information on messages, see Messages.

The number of burstDone`N` output ports is defined by the parameter. burstDone`N` represents the `N`th input port

Data Types: `BurstRequest`2

Parameters

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Hardware board — View or modify current hardware settings

name of current hardware board

This parameter is read-only.

This parameter shows a link to the selected hardware board. Click the link to open the configuration parameters, and adjust the settings or choose a different board.

To learn more about configuration parameters for the memory controller, see .

Main

Memory selection — Choose between memory regions

`BurstRequest`8 (default) | `BurstRequest`9

Select between processing subsystem (PS) or programming logic (PL) memory.

• If the selected board supports only a PL memory, then the default value is `BurstRequest`9.
• If the selected board supports only PS memory or only PL memory, then this parameter is read-only.
• If the selected board is not a supported SoC board, then this parameter is not visible.

Number of masters — Number of masters connected to this controller

`BurstAccepted`1 (default) | positive integer

Set this parameter to generate the interface accordingly, and specify how many masters connect to the memory.

Advanced

Interconnect arbitration — Arbitration policy

`BurstAccepted`2 (default) | `BurstAccepted`3

Set the arbitration policy for the memory-interconnect block. When multiple masters request for memory access, the policy is determined by the value of this parameter.

• `BurstAccepted`2 sets a fair arbitration based on last service time.
• `BurstAccepted`3 sets a fixed priority of burstReq1, burstReq2, burstReq3, and so on, where burstReq1 gets the highest priority.

Use hardware board settings — Use hardware implementation settings from the configuration parameters

`BurstAccepted`6 (default) | `BurstAccepted`7

Select this parameter to use the same model-wide settings as set in the configuration parameters. Clear this parameter to customize the settings for this memory controller. When using customized settings, values are still checked against hardware-specific constraints. For more information, see FPGA design (mem controllers).

Bandwidth — Bandwidth for transactions towards external memory

scalar

This parameter is read-only.

This value shows the calculated bandwidth between the memory controller and the external memory. It is calculated as Frequency (MHz) multiplied by Data width (bits).

Frequency (MHz) — Controller clock frequency, in MHz

`BurstAccepted`8 (default) | scalar

The clock rate of the bus used to drive interactions with the external memory. The controller frequency determines the overall system bandwidth for external memory that must be shared among all the masters in the model.

Dependencies

To enable this parameter, clear the Use hardware board settings parameter.

Data width (bits) — Bit width of datapath

`BurstAccepted`9 (default) | positive integer

Set the width, in bits, of the datapath between the memory controller and the memory interconnect.

Dependencies

To enable this parameter, clear the Use hardware board settings parameter.

Bandwidth derating (%) — Memory transaction inefficiencies

0-100

Model memory transaction inefficiencies specified by a derating percentage value. For every 100 clocks, memory transaction execution is paused for the number of clocks equal to Bandwidth derating. To set this parameter, measure the maximum bandwidth on your board and reflect the bandwidth derating from your board in this parameter. See an example in Analyze Memory Bandwidth Using Traffic Generators.

Dependencies

To enable this parameter, clear the Use hardware board settings parameter.

Request to first transfer (in clocks) — Number of clock cycles between request and start of transfer

nonnegative integer

Specify the delay, in clock cycles, between a read or write request and the start of a transfer. Specify nonnegative integer values in both Write and Read boxes.

This delay is the number of clock cycles between making a request to the memory controller and until it returns a response. It is reflected in the Logic Analyzer waveforms as the time that the memory controller state remains as`BurstAccepted`. For more information about viewing waveforms in simulation, see .

To set this value, measure the clock cycles between the burst-request and start of transfer on your board. For instructions for extracting this information from a hardware execution, see .

Dependencies

To enable this parameter, clear the Use hardware board settings parameter.

Last transfer to transaction complete (in clocks) — Number of clock cycles between the end of transfer and completion of transaction

nonnegative integer

Specify the delay in clock cycles between the end of a memory transfer and the end of a transaction. Specify nonnegative integer values in both Write and Read boxes.

To set this value, measure the clock cycles between the end of the burst and the completion of the transaction on your board. For instructions for extracting this information from a hardware execution, see .

Dependencies

To enable this parameter, clear the Use hardware board settings parameter.

Performance

Click Launch performance app to open the Performance Metrics window. For additional information, see Simulation Performance Plots.

Extended Capabilities

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

To automatically generate HDL code for your design, and execute on an SoC device, use the SoC Builder tool. See Generate SoC Design.