Which device is used to extend the range of wireless communication infrastructure?

Platform-Host Communications Interface

The purpose of this platform is to interface with an external processing unit, specifically a general-purpose computer. There is a trend in wireless infrastructure design toward increased modularity. The interface between the radio front end and digital signal processing units is becoming increasingly well defined. Two developing and similar interface standards are the common public radio interface (CPRI, supported by Siemens, Ericcson, Huawei) and the open base station architecture initiative (OBSAI, supported by Nokia, Samsung, Hyundai). Given this partition, the performance of the interface is critical to overall system performance. When considering the impact of the performance of this data link, a number of factors need to be taken into consideration:

Maximum sustained data rate (Mbps), after link management overhead.

Latency or transport delay.

Data sample resolution on receive and transmit channels.

Clock recovery encoding.

Control channel for reconfigurable radio platforms.

Number of independent transceivers (multiple-input, multiple-output systems).

Several of these are defined by the link technology chosen or the target communication mode; however, forward error correction and data sample resolution are influenced by design choices. Earlier it was noted that, for the receiver, a high-resolution ADC could substantially ease the design of the band-select filters; however, an implication of this is that these higher-resolution data samples must be transferred to the signal processing unit across this data link or else truncation results in an effective loss of sensitivity. The transmitter on which the signal is being generated and any quantization noise due to limited numerical resolution experience the same attenuation as the transmitted signal. However, without strong filters at the antenna, it is important to minimize any potential out-of-band noise. A second design choice is whether to embed a high-quality clock into the data. When dealing with any RF front end, it is important to ensure that the system is precisely frequency controlled; delivering a high-quality frequency reference through the data to all base stations is a convenient choice and one proposed in the CPRI/ OBSAI standards. Such a clock can be embedded in several ways, but one of the most popular is to use symbol mapping. One such scheme is 8b/10b encoding, where 8 bits are maps to a 10-bit symbol, with a 25% overhead. These design choices have a significant impact on the required performance of the data link, as is shown by the examples given in Table 19.3.

Table 19.3. Platform Interface Communications Requirements

For the application we use 16 bits in each direction to provide the necessary receive sensitivity and minimum out-of-band noise. We choose not to utilize clock embedding. For our target of a 70 MHz bandwidth, a data rate of approximately 10 Gbps is beyond the scope of any standard PC interface. In 2006, the best choice we had available was USB2, which had a maximum sustained throughput of about 380 Mbps, allowing us a bandwidth of about 3 MHz (simplex) or 1.5 MHz (duplex). Modifying the sample resolutions allows us to double the throughput. This was a fundamental performance bottleneck for the platform with only two solutions: place a processor or FPGA on the board or use a higher-performance link. For the initial development, these options were not pursued and the RF performance was throttled to match the USB interface.

18.3.2 DSP Plus ASIC and the Evolution of a High Bandwidth Interface

In the 1990s, the DSP chips were connected to the FPGAs or operator-developed ASICs using a memory interface, simply because that was available on the DSP. As DSPs became more common in wireless infrastructure, there was a recognized need for a more efficient interface between the DSPs and the ASIC/FPGA, as well as between DSPs. The industry gradually moved toward RapidIO as a solution. RapidIO is a peer-to-peer protocol, which initially came from the military space, with both an address-based format as well as a packet-based format. Connection between the DSPs quickly moved to RapidIO as the DSPs started to support it, but interconnection to the FPGAs often remained as a memory interface as the FPGAs did not support RapidIO as a hard macro, and therefore, RapidIO remained an expensive interface on the FPGA side. FPGAs supported PCI Express because of its connection to Intel processors, but this was not suitable for the kind of low latency, high reliability, and peer-to-peer connection required in wireless infrastructure. For a somewhat biased, but essentially correct, analysis of RapidIO versus PCIExpress, see Ref. [38]. In this article, there is also a comparison to Ethernet. In this case, the difference to RapidIO is not so severe and there exists a desire among chip developers that Ethernet could replace RapidIO, even if it is not quite as efficient, because we could then take advantage of lower cost Ethernet routers, as well as reduce the number of routers and lines on the modem card, as Ethernet has to be supported anyway. But this has yet to happen in the majority of chips for wireless infrastructure.

The other main interface on the wireless modem chip is the Common Public Radio Interface (CPRI), which is designed exclusively for the antenna data. This interface was standardized in order to allow different RF equipment to talk to the same baseband modem card. It was hoped that this would reduce the cost and increase flexibility in the network. It had a competitor standardization effort called Open Base Station Architecture Initiative (OBSAI) [6] that was generally less successful. The problem with both standards remains the use of a frame format for the data (see Fig. 18.3). This was adopted because it was how antenna data was usually input in proprietary formats, but also because it was seen as a low timing jitter solution. Low timing jitter is a critical requirement for antenna data as it is in the critical path of signal processing. However, this meant that the standard was inflexible to changes and different variants had to be added to support GSM, CDMA, WCDMA, WiMax, and LTE. Additionally, the addition of control and Ethernet over RapidIO led to more complexity. CPRI also suffered from many different formats to support individual OEM requirements, meaning that it was not tremendously interoperable. It is the authors’ opinion that a packet-based protocol would have much more flexibility and a much lower gate count on the chip, and the jitter issue could be managed. But, at this time, CPRI will be the protocol for some time to come.

15.7 CONCLUSION

Information assurance techniques employed in wired networks have limited direct applicability in wireless networks because of the unique aspects of wireless networks (user mobility, wireless channel, power conservation, limited computational power in mobile nodes, and security at the link layer). In this chapter, we study the survivability and security in wireless networks, both for hybrid wireless infrastructure networks and wireless ad hoc and sensor networks. The issues that are related to the interaction between survivability and security in hybrid wireless infrastructure networks are discussed. We provide a framework that can be used to understand the implications of failures or security breaches on the performance and design of hybrid wireless infrastructure networks. We also address the design issues for secure and survivable wireless sensor networks, which are vulnerable to physical and network-based security attacks, accidents, and failures. Based on the study about the security requirements and survivability requirements, we develop architecture for security and survivability in WSNs with heterogeneous sensor nodes. To better understand the interactions between survivability and security, we also design and analyze a key management scheme within the architecture. The experiment results show that a good design can improve both security and survivability of WSNs. It also illustrates that there is a trade-off between security and survivability in some scenarios.

Other Skill Areas and Responsibilities

Clinical engineers should work with local, regional and professional leadership to upgrade job descriptions to support the special operational needs of a disaster situation, including:

Managing local/regional Emergency Operations Center information as Situation Specialist

Filter and communicate incoming info for Common Operating Picture

Diagnosis and remediation of wireless infrastructure in local and alternate sites of care

Conduct damage assessment rounds to validate operational state of medical device infrastructure

Workflow engineering for alternate sites of care

Remote patient monitoring

Mobility workflows for disaster situations

Ham radio services; supplementary communications channels

Alternate supply-chain management

Credentialing and access control to sensitive areas

Patient and staff identification, tracking technologies linked to vital signs monitoring

Extension of emergency infrastructure: power, device transfer, connectivity to remote sites

Register and manage volunteer teams for disaster response

Manage surge-site setup.